1. Technical Field
Various embodiments of the present invention relate to a semiconductor device and, more particularly, to a semiconductor device having a storage node contact and a buried gate structure.
2. Related Art
Although the demand for large capacity semiconductor devices has grown in recent years, an increase in capacity of dynamic random access devices (DRAMs) has reached its limit due to a limitation on the ability to increase chip size. When the chip size is increased, the number of chips per wafer is reduced, and thus the device fabrication productivity is reduced. Therefore, efforts to reduce cell area by changing the cell layout have been made with the goal of integrating as many memory cells into one wafer as possible.
As the semiconductor devices become more highly integrated, the size of the semiconductor devices formed on a chip are reduced. Particularly, areas of storage node contacts and bit line contacts that are formed in active regions between gates are increasingly reduced, and contact resistance is increased, resulting in electrical characteristics that are degraded.